Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics
International Journal of Recent Technology and Engineering
Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.
Sai Venkatramana Prasada, G. S.; Seshikala, G.; and Niranjana, S., "Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics" (2019). Open Access Archive. 688.