Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics

Authors

G. S. Sai Venkatramana Prasada, Srinivas University
G. Seshikala, REVA University
S. Niranjana, Manipal Institute of Technology

Document Type

Article

Publication Title

International Journal of Recent Technology and Engineering

Abstract

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

First Page

1064

Last Page

1067

DOI

10.35940/ijrte.B1199.0782S319

Publication Date

7-1-2019

Recommended Citation

Sai Venkatramana Prasada, G. S.; Seshikala, G.; and Niranjana, S., "Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics" (2019). Open Access archive. 688.
https://impressions.manipal.edu/open-access-archive/688