Digital system design for processors

Document Type

News Article


In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low-power, high-speed blocks. The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. The present work discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a two-phase clocked sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated into the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches. The image processed through the new architecture has been quantitatively analyzed.

Recent publications related to the work with weblinks

  1. doi: 10.35940/ijrte.B2110.078219
  2. doi: 10.1109/ACCESS.2021.3058736
  3. doi: 10.24425-ijet.2022.139883/970
  4. https://doi.org/10.22068/IJEEE.19.1.2391

Publication Date

Spring 10-1-2022